In integrated circuits, parallel conductive lines are widely used to interconnect circuit elements. FIG. 1 shows conductive lines 120 formed on a substrate 101, separated by line spaces 135. The width of the line spacing and conductive line is referred to as the “line pitch”. A limiting factor to reducing the line pitch is the minimum resolution or feature size (F) of a specific lithographic tool. With the line spacing and line width equal to 1F each, the minimum line pitch is 2F.
One technique for reducing line pitch below 2F is to provide an additional level 165 on which second conductive lines 125 are formed. By staggering the lines between first and second levels 160 and 165, a line pitch of less than 2F can be achieved. Reducing the line pitch is desirable since it reduces chip size, thus reducing manufacturing costs since more chips can be fabricated on a wafer. However, when the line pitch is reduced, the line capacitance increases due to the larger line-to-line capacitance. Larger line capacitance is undesirable as it increases power consumption. In addition, the larger line capacitance can negatively affect the signal integrity due to coupling noise from neighboring lines, reducing yield.
As evidenced from the foregoing discussion, it is desirable to reduce the line pitch in order to reduce the chip area. In addition, it is desirable to reduce the line-to-line capacitance and the total line capacitance for a given pitch.